BSDCan2010 - Final Release
BSDCan 2010
The Technical BSD Conference
| Speakers | |
|---|---|
|
Luigi Rizzo |
| Schedule | |
|---|---|
| Day | Talks - 1 - 2010-05-13 |
| Room | DMS 1160 |
| Start time | 14:30 |
| Duration | 01:00 |
| Info | |
| ID | 201 |
| Event type | Lecture |
| Track | Hacking |
| Language used for presentation | English |
A new packet scheduling architecture for FreeBSD
Historically, FreeBSD has had two packet scheduling options: AltQ, which can do output scheduling using the network card as a transmission clock, and "dummynet", which was born as a link emulator but also included one scheduling algorithm.
We have recently made an almost complete rewrite of dummynet to support multiple scheduling algorithms, so that users can pick the ones that fit best their needs. In the process, we also performed a thorough performance analysis of the tool, so now users can make more informed choices on how to configure their packet scheduling/shaping architecture and on which tradeoffs are involved.
In this talk we will make the following contributions:
- describe the internal architecture of the new version of "dummynet", and the API used by the loadable packet schedulers;
- give a "user view" of the new features made available by this updated version of dummynet;
- briefly discuss the theory behind packet scheduling, and show how different solutions expose different tradeoffs betweeen service properties, guarantees and run-time complexity;
- show a number of examples and experiments, running real code from the SVN tree, to demonstrate that the (apparently dry) theory discussed in #3 has actual implications in practice.